Coordinate conversion system for strap down inertial guidance systems



Jan. 25, 1966 R. R. WILLIAMSON 3,231,726

COORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMSFiled June 22, 1961 10 Sheets-Sheet 1 INVENTOR.

ROB T WILLIAMSON BY r ATTORN EY Jan. 25, 1966 R. R. WILLIAMSON 3,231,726

COORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMSFiled June 22, 1961 l0 Sheets-Sheet 2 FIG. 2

LINEAR 1 ACCELERAT'ON I BASIC COMPUTER CONFIGURATION I EENSORS I I I 7I0 I r I AX It) A X (t) I ACCELEROMETER I 1' a2 I13 I I I I2 I I I l M(t) A Y (t) I ACCELEROMETER I BI B2 33 I I I I I m 1 I l A i (t) IACCELEROMETER I A (t) 72 73 I l l J I I RATE-OF-TURN a a2 I %J I I RD EI M I I 6 GY I I (1 =w (I -my 1 I! I l l l I l GYRO I a =wx a w 3 I1|---l l i I I i I I I 73% I I l l y FIG. 4

Jan. 25, 1966 R. R. WILLIAMSON 3,231,726

COORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMSFiled June 22, 1961 10 Sheets-Sheet 3 FIG. 5 FIG. 6

a) o E (D m o O 9 6 r n+| n n+| SINE GENERATION COSINE GENERATION FIG. 7FIG. 8

Q U) z I 5 8 9 n Pn (n+1) n Qn (n+|) SINE GENERATION COSINE GENERATION25, 1965 R. R. WILLIAMSON 3,231,726

COORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMSFiled June 22. 1961 10 Sheets-Sheet 4 FIG. 9

A% -"R"REMAINDER REGISTER ADD *-Ax I "Y"ADDEND REGISTER -A FIG. IO

A n+I REGISTER"R"(REMAINDER o A S REGISTER "Y (Sn) FIG, H

A S REGISTER "R" (REMAINDER S Ac REGISTERY" (o Jan. 25, 1966 R. R.WILLIAMSON Filed June 22, 1961 FIG.

l0 Sheets-Sheet 5 /IOO REGISTER"R"(REMAINDER 0n) REGISTER"Y"(S ASn+IADDER CARRY FLIP FLOP a ADDER lIO REGISTER "R" (REMAINDER Sn) REGISTER"Y"(C 2 lH-l I Ch ADDER CARRY FLIP FLOP 8 Cn 8 ADDER Jan. 25, 1966 R. R.WILLIAMSON COORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCESYSTEMS Filed June 22. 1961 10 Sheets-Sheet 6 FIVE MODULES (I (1 1 miCHECK FIVE MODULES B, B B A); CHECK FIG. I3

FIVE MODULES 7, 7 7 CHECK FIG. I4 (I, MODULE OVERFLOW Au, ONLY LOGIC I32oNE-INcREIvIENT I30 ADD-SUBTRACT NETWORK JV or ADDEND REGISTER To OTHERMODULES 1 REMAINDER REGISTER CRITICAL CONDITION SCANNING A LOGIC(F|G.20)I22 I f I RoIvI CHECK A MODULE (Q2) INPUT FOUR INPUT 1 (FIG.23)

n LOGIC ADDER-SUBTRACTOR IoGI (F|G.l6) (FIG. I5)

I26 OVERFLOW P (8y) coRREcTIoN LOGIC in (FIGs. l7-l9) Jan. 25, 1966COORDINATE '0 Filed June 22, 1961 FROM INPUT LOGIC FIG. I6 INPUT LOGIC RR. WILLIAMSON ONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMSDELAY REGISTER I-BIT ca DELAY REGISTER I-BIT (C2)" AND AND

AND

(0: I m L AND (Fl 6. 20) v I AND (F! s 20) V AND (FIG. I?) (c) AND I(-I) I" AND I (FIG. I9) (C) --I- 10 Sheets-Sheet 7 FOUR INPUTADDERSUBTRACTER I22- TO Rai REGISTER Act,

0 ER LOW TO SUMMER -I50- (FIG. I5)

CORRECTION TERM Jan. 25, 1966 R. R. WILLIAMSON 3,231,726

COORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMSFiled June 22, 1961 10 Sheets-Sheet 9 FIG. 20 CRITICAL CONDITIONSCANNING LOGIC I28 A TOINPUT I v fi LOGIC I24 FLIP FLOP 266 V (FIG. I4)

v W Po (Ch) AND TO LOGIC 264 OR FROM NETWORK|3O CHECK MODULE FIG. 14)

250 AND 252 AND I (C) (FlG.I7 n (C) (FIG.l8) s, 3 I 2 2 FLIP FLIP FLOPFLOP 8 2 254 256 7 P2I AND AND 258 AND AND 27o FIG.2I AXMODULE REMAINDERRAX REGISTER or 'NPUT FOUR INPUT 2 a NETWORK ADDER SUBTRACTOR I(OVERFLOW ONLY) Jan. 25, 1966 Filed June 22, 1961 R. R. WILLIAMSONCOORDINATE CONVERSION SYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMS 10Sheets-Sheet 10 United States Patent 3,231,726 COORDINATE CONVERSIONSYSTEM FOR STRAP DOWN INERTIAL GUIDANCE SYSTEMS Robert R. Williamson,Carlsbad, Calif., assignor to General Precision, Inc., a corporation ofDelaware Filed June 22, 1961, Ser. No. 118,981 9 Claims. (Cl. 235-164)The present invention relates to coordinate conversion Systems, and itrelates more particularly to an improved inertial guidance system of thestrap-down type, which does not require a stable platform, and in whichvehiclereferenced coordinates are converted to selected-stabilizedcoordinates by incremental computer means.

Inertial guidance systems are utilized in manned vehicles, such asaircraft, ships and submarines; and in unmanned vehicles, such asmissiles, to provide an automatic navigation system for the vehicles.The automatic navigation system functions to sense changes in speed ofthe vehicle with respect to selected-stabilized axes, and to produceoutput signals corresponding to such changes. The output signals may beused in the guidance system to initiate appropriate controls for thevehicle so as to guide the vehicle along a predetermined course inspace.

Most prior art inertial guidance systems include a stable platform whichis gimbal supported to be angularly independent of the vehicle in whichthe system is mounted. The stable platform of the prior art systems isheld angularly fixed in space, so as to provide a stabilized referencefor the system.

The stable platform type of prior art inertial guidance system, such asdescribed above, exhibits certain inherent disadvantages due to themechanical complexity of the stable platform mechanism, and due to thedrift tendencies of such platforms. The mechanical structure adds to thesize, weight and cost of the guidance system and reduces itsreliability.

The present invention provides an inertial guidance system in whichinertial measurements as to the change of angular motion of the vehicleare made with respect to selected vehicle-fixed axes of the vehicleitself, rather than with respect to a stabilized platform. This is thebasis for the term strap-down system, since the acceleration sensinginstrumentalities and the angular change sensing instrumentalities aremounted directly on the frame of the vehicle itself and are not underthe control of a stable platform.

It is, accordingly, an object of the present invention to provide animproved inertial guidance system for a vehicle which is of thestrap-down type, and which does not require stabilization by a stableplatform, or equivalent instrumentalities.

Another object of the invention is to provide such an improvedstrap-down inertial guidance. system which includes a computer forutilizing signals from the acceleration and rate-of-turninstrumentalities mounted on the frame of the vehicle, and to provideoutputs representative, for example, of the vehicle accelerations withrespect to selected stabilized axes.

The particular computer to be described in the ensuing description ofthe invention as suitable for use in the strap-down guidance system ofthe invention, is a transistorized, high speed, modular, incrementalcomputer. The computer operates in conjunction with linearacceleration-sensing instrumentalities and angular rate-sensinginstrumentalities, which, as mentioned above, are mounted directly onthe frame of the vehicle. The computer provides stabilized signalsrepresenting vectors of vehicle acceleration with respect to the axes ofa selected stable coordinate system.

- The particular incremental computer to be described operate inparallel. A feature of the system to be described is that these modulesare freely interchangeable with one another so as to facilitate theconstruction and service of the computer.

The operating frequency of the incremental computer to be described maybe of the order of one megacycle, and it has the capability to exhibit asolution rate of fifty thousand solutions per second. The transistorizedcomputer may be excited directly from a 28 volt battery, and it mayoperate on approximately 75 watts of power. The computer memory may becomposed of l-word magnetostrictive delay lines. The weight of thecomputer may be of the order of 5-7 pounds, and its size of the order of0.1 cubic feet.

In brief, therefore, the principal objects of the present invention areto provide a low cost, light weight, small size, strap-down inertialguidance system which is capable of precisely and accuratelytransforming measurements in a vehicle-fixed coordinate system to valuesin a spacestabilized coordinate system, and which has the ability tocope with relatively large linear and angular accelerations of thevehicle.

The modular approach to the embodiment of the invention to be describedis possible due to the particular difference equations selected forsolution by the incremental computer. These equations represent thedirection cosines of a matrix which resolves the vehicle-fixedcoordinates to stabilized coordinates.

The selection of these particular difference equations makes it possibleto organize the incremental computer in a straightforward and practicalmanner into a means for solving three separate and independent, butidentical, problems. Therefore, the strap-down system of the inventionmay take the form of three separate, identical computers, operating inparallel. Alternately, the system of the invention may take the form ofa single computer which solves the three separate problems on a serialtimeshared basis.

When the three separate computers are used, each of the three may becomposed of five identical modules, to provide a system made up offifteen identical modules. When the single computer is used, thesolutions required may be derived from five modules operating on atimeshared basis.

The above-mentioned use of identical modules permits interchangeability,which, as noted, facilitates to a large extent the construction andservicing of the computational system. For example, since the modulesare mutually interchangeable, all efforts as to reliability, economy,and the like, can be concentrated on a single module; and the benefitsof these concentrated efforts can be reflected throughout all theplurality of modules in the computational system by mere duplication.

In addition to the benefits mentioned in the preceding paragraph, theservicing of the module-type computational system is greatlyfacilitated. This is because the usual- 1y required multiplicity ofspare parts can be replaced by standpoint This use of identical modulespenmits reincludes fifteen, similar, serial incremental modules whichdundant modules to be included in the computational system, with anautomatic switch-over control being pro vided for switching a redundantmodule into the system in the event of a malfunction in any of theoperative modules.

The strap-down inertial guidance system to be described is capable, notonly of providing all the capabil ities of inertial guidance systems,but also for providing inverse resolutions, for example, as needed forthe generation of control signals in missile guidance systems.

These ancillary features can be realized by the provision of identical,additional incremental modules in the computational system.

It will also be evident as the description proceeds, and as indicatedabove, that the inertial guidance system of the invention is not limitedto airborne applications, but can find practical use in many differenttypes of vehicles, including land and sea vehicles. In fact, theimproved system of the invention can find utility in any applicationwhere the precise and efficient conversion from one coordinate system toanother is required.

In the drawings:

FIGURE 1 is a representation of the vehicle-fixed and stabilizedcoordinate systems and of the manner in which the direction cosines areresolved;

FIGURE 2 is a schematic block diagram of one embodiment of the system ofthe invention;

FIGURE 3 is an action diagram illustrating an angular increment in atwo-dimensional system and which is useful in explaining the presentinvention;

FIGURE 4 is a vector representation of an inherent error in theincremental generation of sines and cosines, and which error iseliminated in the system of the invention;

FIGURE 5 is a schematic representation of the box-car incrementalgeneration of a sine;

FIGURE 6 is the schematic representation of the boxcar incrementalgeneration of a cosine;

FIGURE 7 is a schematic representation of the trapezoidal incrementalgeneration of a sine;

FIGURE 8 is a schematic representation of the trapezoidal incrementalgeneration of a cosine;

FIGURE 9 illustrates schematically a basic incremental computer unit;

FIGURES 10 and 11 illustrate schematically the basic incrementalcomputer unit as applied to the system of the invention;

FIGURE 12 is a more complete block representation of the incrementalcomputer units applied to the system of the invention;

FIGURE 13 is a schematic showing of the different modules incorporatedinto the embodiment of the invention to be described herein;

FIGURE 14 is a block representation of the logic and other componentsincluded in one of the modules of FIGURE 13;

FIGURE 15 represents suitable logic for an add-subtractor included inthe module of FIGURE 14;

FIGURE 16 represents suitable input logic for the module of FIGURE 14;

FIGURES 17-19 represent connection logic for the module of FIGURE 15;

FIGURE 20 is a logical representation of a system for determining when aregister in the module of FIG- URE 14 is in a critical condition;

FIGURE 21 is a logical representation of another module for use in thecomputer of the invention;

FIGURE 22 represents suitable input logic for the module of FIGURE 21;and

FIGURE 23 is a typical representation of a check module used in thecomputer of the disclosed embodiment of the invention.

The computational system of the invention in its broader aspects, asnoted above, serves to transform a first coordinate system, such as avehicle-fixed coordinate system, to a second selected-stabilizedcoordinate system. This transformation, as will be described, isachieved by solving the difference equations representing the directioncosines between the vehicle-referenced coordinate system and theselected stabilized coordinate system.

In order that the system of the invention may perform the coordinatetransformation referred to in the preceding paragraph, signalsrepresenting the total angular rate of the vehicle-fixed coordinatesystem with respect to the stabilized system, are input to the system.Further signals representing the accelerations of the vehicle withrespect to the vehicle-fixed coordinate system are introduced to thecomputational system. The resulting computed outputs are representative,for example, of the vehicle acceleration vectors with respect to theselectedstabilized coordinate system.

It is evident that in order to preclude the necessity of orienting thevehicle itself prior to launching to a particular initial positioncorresponding to the pre-selected coordinate system in space, signalsrepresentative of certain initial conditions must be fed into thecomputational system of the invention. Then, the actual transformationperformed by the system of the invention will be with respect to apre-selected stabilized coordinate system.

The initial condition settings referred to above are equivalent to theinitial adjustments of the stable platform in the prior art stabilizedplatform type of initial guidance system. In the prior art stableplatform type of initial guidance system, the stable platform isinitially set to a pre-determined position by the introduction oftorquing signals to its gimbal-controlled servo mechanism. Thesetorquing signals serve, for example, to set the platform to apre-determined heading and attitude prior to launching. However, theinitial condition setting signals can be introduced instantaneously intothe system of the invention, and no warm up period is required, as isthe case with the prior art stable platform systems.

Because of this Warm-up factor, the prior art stable platform type ofguidance system is unsuitable for use in missiles, and the like, whichmust be kept at the ready for prolonged intervals of time. Such missilesmust be in such as operative condition, that upon the appropriatesignal, they may be instantaneously launched. However, the amount oftime normally required to adjust the stable platform of the prior artguidance system to its initial condition is relatively long. This meansthat for instantaneous readiness, the prior art stable platform must beset and ready in the prior art guidance system which, in turn, meansthat the torquing signals must be continuously applied thereto and thewhole mechanism must be actually in mechanical operation. This, ofcourse, is impractical over prolonged periods of time.

As described above, the computation system of the present inventionusually must also have certain initial conditions preset into it. Thispre-setting of the system of the invention, as also described above, isto permit the coordinate transformation to be effectuated with respectto a selected stabilized coordinate system. For example, an appropriatestabilized coordinate system would be an earth-centered system.

In the case of the computational system of the present invention, theinitial conditions are pre-set into the system merely by introducingsignals representative of certain digital numbers. These numbers arecomputed on the basis of the relationship between the location andorientation of the particular vehicle and the different axes of theselected fixed coordinate system. The initial setting signals can beintroduced instantaneously into the computational system of theinvention at the moment of launching.

Therefore, the system of the present invention is ideal for use inmissiles, and the like, since it can be maintained ready forinstantaneous use; without the need for activating mechanically movableparts over prolonged periods of time, as would be the case with theprior art stable platform systems.

The inertial sensors to be used in the system of the invention, asapplied to inertial guidance, include, for example, a group of threeaccelerometers for sensing linear accelerations along three axes whichare fixed with respect to the vehicle; and a group of three rate gyrosfor sensing angular rates about the three vehicle-fixed axes. Thecomputer included in the guidance system readily accepts pulse typeinformation, and for that reason, the outputs of the rate gyros and ofthe accelerometers should preferably have a digital incremental form.

Inertial sensors of the incremental digital type are described, forexample, in the Handbook of Astronautical Engineering, Koelle,McGraw-Hill Publishing Company, First edition, 1961 (13-3). Reference isalso made to Computer Handbook, Husky and Korn, McGraw-Hill PublishingCompany, 1962 (19-55).

As noted above, the system of the invention may be composed of threeseparate incremental computers all operating in parallel to solve thethree separate, but identical, problems. When this parallel approach isused, fifteen serial-incremental modules are used. Nine of these modulesare used to generate the direction cosines; three are used to multiplythe direction cosines with representative measured accelerations to formthe stabilized components of acceleration; and three serve as checkmodules to assure that there are no erroneous variations in therespective magnitudes of the three vectors.

As also noted, the system of the invention may be composed of a singleincremental computer which solves the three problems in a serialtime-shared manner. This computer would be composed of five modules,three being used to generate the direction cosines in a serial manner;one being used serially to multiply each direction cosine with thecorresponding acceleration; and one being used in a serial manner as thecheck module.

The basic equations to be solved by the computational system of theinvention may be derived as follows:

In FIGURE 1, the axes x, y and z are intended to represent the axes ofthe vehicle-fixed coordinate system; and the axes x, y and z' areintended to represent the axes of the stabilized coordinate system.

If the unit vectors along the vehicle-fixed axes are representedrespectively by ordinate system will be the vector sum of the measuredangular velocities. That is:

where the subscripts D and M denote with respect to the space-stabilizedand vehicle-fixed coordinate systems, respectively. But, by definition,the term and if the unit vectors along the stabilized axes berepresented respectively as In the above equations, and with referenceto FIG- URE 1 'The 1, 2! 3: 51, B2: B3 71 "/21 73 will be referred to inthe following description as the direction cosines.

;'.The rate gyros of the system, as mentioned above, and as will bedescribed in more detail, provide instantaneous angular velocityreadings about the three vehicle fixed axes x, y, z. These angularvelocities will be represented as ta m w respectively. Since thestabilized coordinate system is fixed in space, the angular velocity 5between the vehicle-fixed coordinate system and the stabilized co- 1s aunit vector.. Therefore:

also

x I A a "a M l 2 y+ 3 z where 5 is the rate of change of the directioncosine 02 0: is the rate of change of the direction cosine 0Z a is therate of change of the direction cosine a Therefore:

=( z 2- y z) x+( x awzm) y+( y r-wx efl; (5)

Equation 5 yields the first three basic equations i=azwzaaw & =a w a w,

V & =a w a wx Similar derivatives Z and Z? give the remaining basicequations:

fil B2 z B3 y Bz=t awxB1 t (1 fia=fi1 y fi2 x 'i1 'Y2-z-73 y 'l 2='Y3 x'yl z 3) 'lfa='Yl y 'Yzwx The measured components of the accelerationsalong the three axes of the vehicle-fixed coordinate system may berepresented as AMI), A), Az'(t).

The system of the invention provides output signals representative ofthe components of these accelerations in inertial stabilizedcoordinates, as referenced to the stabilized coordinate system. Theselatter components are represented as AX(t), AY(t), A20).

The latter components are obtained by the rotation operation AX a a aAri Y 515253 p (1 Z 'Y1'Y2'Y 7 where the ,8 and 'ys are theinstantaneous values of the direction cosines.

It is, therefore, necessary first to complete the direction cosines fromthe basic Equations 6-14, and then to compute the sums Ai', A1], A2...

An inertial guidance system embodying one embodiment of the invention isillustrated schematically in FIG- URE 2. The basic computerconfiguration illustrated therein includes a block 50 and a block 52.The linear acceleration sensors are represented by three accelerometers,which, in turn, are represented by the blocks 10, 12 and 14. Theseaccelerometers, as mentioned above, are mounted to measure accelerationsalong the vehiclefixed axes, and they are orthogonally related to oneanother. As noted above, the accelerometers are preferably of theincremental digital type, so that outputs may be directly used by theincremental computer of the system. As also mentioned above, this typeof accelerometer is described, for example, in Section 13-3 of theHandbook of Astronautical Engineering, Koelle.

The system of the embodiment of the invention under consideration alsoincludes a group of rate-of-turn sensors, which, in turn, arerepresented by three gyros 16, 18 and 20. These gyros are shown in blockform, as they can have any suitable known construction. The gyros 16, 18and 20 measure the rate of turn of the vehicle about the threevehicle-fixed axes x, y and 2. These gyros, likewise, are preferably ofthe incremental digital type, so that their outputs can be used directlyby the incremental computer of the system. The digital output of thegyro may be formed in the manner described in Section 13-3 of theHandbook of Astronautical Engineering, Koelle, referred to above.

As illustrated in FIGURE 2, the accelerometers 10, 12 and 14 produce theterms A43, A1], A2, respectively; whereas the gyros 16, 18 and 20produce the terms w m and w respectively. The computer block 52 respondsto these latter terms to compute the nine direction cosines a a a {3 ,8and 'y v 'y The direction cosine terms are introduced to the block 50which sums these terms with the acceleration terms, in a manner to bedescribed to produce the desired outputs.

The resulting outputs from the computer include signals representing theterms AX, AY, AZ. These output terms are representative of theacceleration of the vehicle, as referenced to the selectedspace-stabilized display coordi- =nate system.

Many approaches to the computation of the directional cosines appear tobe reasonable when first examined. However, most of these approacheshave proven to be impractical for many reasons. For example, many of theapproaches require an excessive amount of equipment, and many involvethe generation of intermediate variables which have ranges extending toinfinity, which, in turn, create scaling and rate problems.

At present, the preferred mathematical approach is one in which thedirection cosines are derived directly, rather than by the generation ofintermediate variables. The basic dilferential Equations 614 are notsuitable for implementation by an incremental computer. The approach ofthe present invention therefore, is based on diiference equations,rather than differential equations; which difference equations aresusceptible to implementation by incremental computers. The followingdiscussion will be based initially on a two-dimensional system, ratherthan a three-dimensional, for simplicity purposes.

Consider, for example, the generation of the direction cosines in atwo-dimensional system. Such a generation involves, in fact, thegeneration of the sine and cosines of the changing angle 0 in FIGURE 3.Assume now that by the two successive solutions by the computer theangle 0 has changed by an increment 6. The exact difference equationsare obtained from the following:

A sin 0:sin (0+6) -sin 0 [sin 0cos 8+cos 0 sin 6] sin 0 (19) A cos 0=cos(0+6)cos 0: [cos 0 cos 6sin 0 sin 6]'cos 0 (20) The exact differenceequations are, therefore:

A sin 0=sin 6 (cos 51)+cos 0 sin 6 A cos 0=cos 0 (cos 6-1)+sin 6 sin 6e(A sin 0) sin 6 (27) e (A cos 0) cos 0 (28) The Equations 27 and 28show that the error is independent of the sign of 5. That is, the erroris cumulative for each computer solution; and the error is notselfcompensating should the angle 6 change opposite directions duringthe successive solutions.

The characteristics of the above-discussed inherent errors can also bedemonstrated by taking the approximate Equations 23 and 24, namely:

AS=C5 AC: -S6

Then, the (n-l-l solution made by the computer is :rl+1 n n n+1 n n TheEquations 29 and 30, re-arranged, yield the following equations inmatrix form:

Now, if we let R cos tp=l, and R sin 11:6, so that and =tan- 5, as shownin FIGURE 4, then:

The above equations show that if the vector swings through an angle 5for a particular solution, the computer actually treats the swing asthrough an angle =tan- 6. Also, for each solution, the vector magnitudeinstead of being constant, increases in accordance with the relationshipR'=(1+6 Then, after it steps in the same direction, we have:

The first source of error, due to the fact that tan- 6 is considered bythe computer as being equal to 8, is not serious. This is because thefirst source of error still corresponds to a rotation and amounts onlyto a minor scale change on the angle. However, the successive increasein amplitude of the vector for each successive solution is a serioussource of error.

The incremental computer generation of sines and cosines is illustratedschematically in FIGURES and 6. As shown, should the angle 9 changebetween the n and n+1 solution by an amount 6, the sine 9 increment isgenerated in accordance with the equation S S =C 6, and the increment isadded to the previous sine 6 value. Likewise, the cosine increment isgenerated in accordance with the equation C -C 6 and added to theprevious cos 9 solution.

The sine and cosine generations described in the preceding paragraph, asmentioned above, give rise to an error which may be represented by avector and which vector rotates from solution to solution and grows foreach successive solution.

The error vector growth can be eliminated in the following manner. Thereis an intermediate solution P,,, Q,,, such as shown in FIGURES 7 and 8,which is midway between the previous n and n+1 solutions. For theintermediate solution u 2 n'l'l Q. 5 n.

7 Therefore, if for an 9 change of 6 we solve to an intermediate pointwe have an intermediate error vector which has a magnitude R which isthen the n+ l vector must be rotated forward from the n vector by anamount 6 l 2 tan 2 This latter term is a better approximation to 6 thantan- 6. The resulting equations are:

Equations 38 and 39 would appear to indicate that trapezoidalintegration, rather than box-car integration, be used to avoid theabove-mentioned errors. These equations, however, raise problems,because we cannot compute C until we have computed S but we cannotcompute'S until we have computed C It would appear, therefore, thatolder values must be used in one or the other of the Equations 38 and39.

At this point it is appropriate to discuss briefly the manner in whichthe basic mathematics of the problem are handled by the incrementalcomputer in the system of the invention. For simplicity, the operationwill first be explained on the basis of the two-dimensional systemdescribed above.

An incremental computer is composed mainly of sets of units whichperform an integrating function. The basic summing unit may beconsidered as including an accumulator, or remainder, register R (FIGURE9), and an addend register Y, together with means for adding thecontents of these registers.

The addition occurs each time a pulse is applied to the line marked Ax.As the number in the addend register Y is repeatedly added to the numberin the remainder regis ter R, the remainder register will overflow fromtime to time. Each time an overflow occurs, a pulse will appear on theoutput line from the remainder register, designated Az. The rate atwhich overflow occurs from the remainder register R depends upon themagnitude of the number in the addend register Y, and in the effectivesize of the remainder register R.

Therefore, the relationship between the number of Az pulses and Axpulses will be where 2 equals the magnitude of the maximum number heldin the remainder register R when overflow occurs and y is the numberheld in the addend register Y.

It will be understood, of course, that the numbers in the registers Rand Y will be in binary digital form. If the Az pulses are summed in athird register, the integral of the right hand side is obtained. Thecoefficient 2- may be considered to be a scale factor in theintegration.

In the problem under consideration, the operation is such that duringeach compute cycle, a single positive or negative Ay pulse will be addedto the number y in the addend register Y, and a single positive ornegative Ax pulse will affect addition or subtraction.

In general, it is desirable to allow the number y in the addend registerY to increase or decrease. Since the Ay input of one integrator unit maybe obtained from the Az output of another, some means must be providedfor causing Az to indicate a subtraction. This would imply a ternarynumber system where Az might be 0, -1, or +1. Since a binary numbersystem is to be used, Az values 1 and +1 only will occur. Therefore, aone overflow on the Az line will mean +1, while the absence of anoverflow (0) will be interpreted as 1. I

The number system which accomplishes the operation described in thepreceding paragraph operates in the following manner: azero in theaddend register Y is represented by a one at the sign digit positionfollowed by zeroes. If zero represented in this way is repeatedly addedto the remainder register R, the remainder register will overflow oneach alternate addition operation. The Az output, when applied as aninput to another summing device, will therefore cause alternateadditions and subtractions to take place with a not effect of zero.However, if the number y in the addend register Y is some positivequantity, the remainder register R will overflow more often than not,with the result that more additions than subtractions will be signalled.When the number in the addend register Y is negative, a zero will appearin the sign digit positionand the number will be in complement form.

The basic incremental computer of FIGURE 9 as adapted for solving thetwo dimensional sine-cosine problem described above, is shown in FIGURES10 and 11. In these figures, the cosine (C at the W solution point isstored in the addend register Y of FIGURE 11 and in the remainderregister R of FIGURE 10, the most significant digits being the formerand the least significant in the latter. In like manner, the sine (S,,)at the N solution point is stored in the addend register Y of FIGURE 10and in the remainder register R of FIGURE 11, the most significantdigits being in the former and the least significant digits being in thelatter.

The angle increments 6 are introduced to the add networks in FIGURES 10and 11. After each solution n, the n-l-l increments appear at theoutputs of the R registers. It will be remembered that these outputsoccur as a one for overflow, and as a zero for no overflow. Therespective outputs are applied to the corresponding addend registers Y.

A more complete representation of a pair of incremental computer units,corresponding to the units of FIGURES 10 and 11, is shown in FIGURE 12.The system of FIGURE 12 includes a first remainder register 100 forstoring the least significant digits C and it includes an addendregister 102 for storing the most significant digits C The system ofFIGURE 12 also includes a remainder register 104 for storing the leastsignificant digits S and it includes an addend register 106 for storingthe most significant digits S The system of FIGURE 112 also includes anadder 108 whose output is coupled to the input of the register 106, andit includes an adder 110 whose output is applied to the input of theregister 100. The adder 110 includes a carry flip-flop 113, and thecarry flip-flop indicates at the end of each compute cycle whether ornot an overflow has occurred from the remainder register 100.

In like manner, the system includes an adder 112 which is coupled to theinput of the addend register 102, and the system includes an adder 114which is coupled to the input of the remainder register 104. A carryflip-flop 116 included in the circuitry of the :adder 114 indicateswhether or not an overflow has occurred from the remainder register 104.

The contents of the addend register 106 are circulated through the adder108, and a 1 is added or subtracted from the contents, depending uponthe state of the carry flip-flop '116. The contents of the remainderregister 100 are circulated through the adder 110, and appropriate logicderives the term -'S 6 so that the desired integration is performed bythe circuitry of the register 100.

Likewise, the contents of the addend register 102 are circulated throughthe adder 112, and a +1 or 1 is added to the contents as determined bythe state of the flip-flop 113.

The contents of the remainder register '104 are circulated through theadder 114, and appropriate logic is provided for introducing the term CB to the adder so that the desired integration may be performed.

In the incremental generator where: i is the sine increment; i is thecosine increment; and 2- is the quantized single increment, comparableto 8 in size.

Thus, we have:

Equations 42 and 43 indicate that, except for a term of the second ordera box-car integration using old values is equivalent to the desiredtrapezoidal integration requiring new (not yet generated) values.However, in view of the quantization of the integrand in the remainderregisters and 104, the inclusion or exclusion of the terms at any onestep will rarely affect the quantized value generated. Therefore, thecorrection terms can be added to the remainder registers 100 and 104,after the increment of the function is generated just as well as before,thereby making the desired trapezoidal integration.

Therefore, in the embodiment of the invention under consideration, the

and

corrections are made to the remainder registers 100 and 104 for eachcomputation step, but by the use of the last generated i and i values.In this manner, the above described cumulative vector growth error isprevented.

It was noted above, that the above-described correction technique ofintroducing previously-generated terms to the remainder registers foreach computation step will rarely afiect the result. However, there arecertain states of the remainder registers 100 and 104 in which theresult will be affected. It is evident, for example, that should theremainder register 100 or 104 have the number 0.11 111 stored in it, anincrement of be added, the resulting overflow would result in anerroneous +1 being added to the least significant digit position of theaddend register 102 or 106. Likewise, should a remainder register have anumber 1.00 000 stored in it, and increment of i,%=1 ort',%=1

be added, the result would be an erroneous 1 being added to thecorresponding addend register.

To avoid the errors discussed in the preceding paragraph, it isnecessary to observe the new remainder for the critical conditions 0.11111 or 1.00 000, during the generation of the new remainder, and if anoverflow condition is found, to reverse the output.

The techniques described above in conjunction with the generation ofsines and cosines in the two dimension system, can be extended to thegeneration of direction 00- sines in the three dimensional system, inthe following manner:

In the incremental generation of the direction cosines, the differentialterms 5 8 6,, are replaced by the difference ter-ms w At, w At, w At.Then the equations be- 13 We note that the matrix 45 has a determinant1+6 +6 +6 which, as in the two-dimensional case discussed above, resultsin an error vector growth from solution to solution. If now we operateon the intermediate vector, as before, we have:

1% ak 1' (01H %1-% (a), a, -%1 (dam $1 ((13).. a 5- (man-1 Where thedeterminant of each matrix is identically so that there is no errorgrowth in the vectors magnitude. The above equations result in thefollowing basic difference equations:

The correction is inserted as an initial value into the three adders ofthe corresponding remainder registers. These adders are the equivalentof the adders 110 and 114 in FIGURE 12. The inputs to the three addersare, therefore:

The fiip-flolp S on the other hand, is set initially false and scansthrough the successive digits of the number R, in the remainderregister. The flip-flop S is set true, therefore, if any digit of thenumber R is diiferent than the least significant digit. Then if the flipflop S is true at the most significant digit of the number R it denotesthat there is no critical condition. However, if the flirpflop S isfalse at the most significant digit of the number R it indicates thatthe-re is a critical condition. For this latter situation, the flip-flopS denotes cn'ticality to a +1 or 1, depending upon whether the flip-flopS is true or false.

The basic modules of the system to be described are used to performthree different functions. These functions include the generation of thedirection cosines for the as, Bs and ys; the generation of velocitypulse increments AX, AY and AZ in space-stabilized coordinates using thedirection cosines; and the performance of check computations for thedirection cosines.

The module configuration to be described has sufiicient flexibility toperform any of the functions mentioned in the preceding paragraph. Thisflexibility is accomplished by appropriate interconnections within eachmodule and between the separate modules but without changing the modulecomponents.

The generation of the direction cosines is represented by the equations:

As noted above, the Equations 51-62 may be solved in a parallel mannerby three separate incremental computers, all operating in parallel. Withsuch an approach, twelve modules are required to solve Equations 51-62,and three additional modules are required to perform the checkcomputations. This approach is represented by the block diagram ofFIGURE 13.

Alternately, and as also pointed out above, the Equations 51-62 can besolved by a single incremental computer composed of five modules. Withthis latter system, the first module would solve Equations 51-53 in aserial manner; at the same time, the second module would solve Equations54-56 in a serial manner; and also at the same time, the third modulewould solve Equations 57- 59 in a serial manner.

The fourth module in the system described in the preceding paragraphwould solve Equations 60-62 in a serial manner; and the fifth modulewould serially perform the three check computations.

Each module in FIGURE 13 will include basically the components of theincremental integrator described in conjunction with FIGURE 9. The abovedescribed overflow method for obtaining the Az output pulses from theremainder (R) register will be used in the embodiment to be described.

The components included in the module are shown in block form in FIGURE14. It will be understood that similar components, inter-coupled in thesame manner, may be included in the (1 1x 13 6 'y 7;), v3 modules. It isfor that reason that only a module will be discussed in detail herein.

As stated above, the generation of the 11 direction cosine is based onthe following equation:

(correction term) (63) This is implemented in the ca module of FIGURE14. The system included in the module of FIGURE 14 includes a ROLremainder register 120. A circulating system for the register 120 isprovided, and the circulating system includes a four inputadder-subtractor 122, which will be described in greater detail inFIGURE 15; and an input logic network 124 which will be described ingreater detail in FIGURE 16.

In accordance with Equation 63, the terms a a 6 and 6 are introduced tothe input logic network 124, and the correction term is also introducedto the input logic network 124 from a correction logic networkdesignated by a block 126. This latter network 126 is made up of aplurality of circuits which are illustrated in detail in FIGURES 17-19.

As described above, certain critical conditions of the Rea remainderregister 120 must be taken care of, and

this is achieved by means of a critical condition scanning logic network128. This latter network will be described in greater detail inconjunction with FIGURE 20. The critical condition scanning logicnetwork 128 received inputs from the correction logic network 126, fromthe corresponding check module which will be described in greater detailin FIGURE 23, and from the output of the adder-subtractor 122. Theoutputs from the critical condition scanning logic network 128 areapplied to the input logic 124, and these outputs take the form of apair of terms V and V.

The overflow A111 of the remainder register is derived from theadder-subtractor 122 and is introduced to a block 130. The blockrepresents Ana complementing logic and is controlled by a term V fromthe critical condition scanning logic 128. The logic network includes aflip-flop with appropriate input logic to permit it to perform acomplementing function when the term V is true. The resulting pulseincrements A04 from the network 130 are introduced to a oneincrementaddsubtract network 132. This latter network is included in thecirculating system for the ca addend register 134. The output from theadd-subtract network 132 also supplies the term m to the other modules.

The a module system of FIGURE 14 includes the Rea remainder register120, and it also includes the 0: addend register 134 which accumulatesthe pulse increments A04 from the remainder register.

The a a and correction term inputs to the four input adder-subtractornetwork 122 correspond to the terms in Equation 63 for the m directioncosine generation. .An overflow from the Rot remainder register 120corresponds to the (Aa term of that equation. Actually, as illustratedin FIGURE 14, and as will be described in more detail in FIGURE 15, theoverflow Ana is taken directly from the adder-subtractor network 122 atP21 bit time at the completion of each compute cycle.

The scan for the critical condition in the remainder register 120, asdiscussed above, is carried out by the critical condition scanning logicnetwork 128, as will be described in more detail in conjunction withFIGURE 20. This scanning is performed on the bits of the multi-digitbinary number fed into the remainder register 120 from the output of theadder-subtractor 122. When the term V is true to indicate a criticalcondition, the scanned bits of the number which has just entered theremainder register 120 are complemented as they enter theadder-subtractor 122 at the beginning of the next compute cycle. If thesignal from the corresponding check module also indicates a condition,the term V becomes true and the overflow pulse (Ao coming out of theadder 122 immediately following the scanned bits is complemented. by theA12 logic 130. The check module indicates the simultaneous occurrence ofa critical condition in other module such that the terms (m and (0L3)are not accurate as applied to the input logic of FIGURE 16. Thecomplementing of the overflow term serves to correct the resulting errorin the addend register 134 of FIGURE 14.

The pulse increments Aa represented by the overflow of the remainderregister 120 are passed to the network 132 so that these increments maybe accumulated in the 04 addend register 134. Therefore, at anyparticular time, the number in the addend register 134 represents themost significant digits of the 1x term, and the number in the remainderregister 120 represents the least significant digits of that term.

The logic suitable for making up the four input addersubtractor network122 is shown in FIGURE 15. The adder-subtractor network of FIGURE 15includes a plurality of analog Kirchoif adders included in a circuitsimilar to that described and claimed in Patent 2,795,376, which issuedJune 11, 1957 in the name of the present inventor. The network of FIGURE15 performs addition and subtraction by analog Kirchoff adders in afeedback configuration, the adders being so organized that the outputsof the individual adders are respectively the sum digit, the first carrydigit, and the second car-ry digit. Similar adders are described, forexample, at pages 269-289 of the publication entitled High SpeedComputing Devices prepared by the staff of Engineering ResearchAssociates, Inc., First edition, McGraw-Hill Book Company, Inc., 1950.It will be obvious, however, that the adder-subtractor 122 may have anyother appropriate known configuration. The basic components of theparticular adder-subtractor network shown in FIG- URE 15 are fouroperational amplifier type adders 150, 152, 154 and 156; and two one-bitdelay registers 158 and 160, which may be flip-flops. The delayregisters are used to store the carries C and C The amplifier typeadders are known and may take any appropriate configuration, as is wellknown to the art. As mentioned above, four input adder-subtractornetworks are known to the art, and the system shown in FIGURE 15represents but one possible embodiment thereof. Other embodiments may beused, as is well known to the art.

The (C delay register 158 stores a carry with a value of 2 :1, and the(C delay register 160 stores a carry with a value 2 :2. Both carries canbe used simultaneously during a given add cycle to give any carry up toa value of 3. The carries are summed with the four inputs in theamplifier adder 150 which functions as a preliminary summer.

The output of the preliminary summer 150 can have any one of eightvoltage levels corresponding to discrete sums from 0 to 7. The actualsum bit for the particular addition cycle is 0 or 1 depending uponwhether the sum from the preliminary summer 150 is even or odd. Theactual sum bit A (0,1) is formed in the amplifier-adder 152. The twocarries are formed from the output of the preliminary summer 150, andthey are delayed one bit time, which i the equivalent to one add cycle,in order to be summed with the inputs of the subsequent add cycle.

The amplifier-adders 152, 154 and 156 are connected in the illustratedmanner and in accordance with known techniques to provide the properbiasing for one another so that each of the adders may perform itsrequired function.

Subtraction of an input in the adder-subtractor 122 is performed byadding the 2s complement of the number. This is accomplished by feedingthe ordinary ls complement of the number at the input and initiallyadding a l to the carry register 158.

The overflow is derived, by looking at the state of the carry registers158 and 160 at the end of each compute cycle, that is, at P21 bit time.For this purpose, the outputs from the carry registers are introduced toan or gate 162, and the output of the or gate is passed through 11 andgate 164. The and gate is enabled at P21 bit time, as shown. Therefore,an overflow condition is exhibited, when either of the carry registers158 and 160 exhibit a 1 at P21 bit time, and this overflow condition ispassed on to the add-subtract network 132 of FIGURE 14 through the logicnetwork 130.

The input logic network 124 in FIGURE 14 performs the functions ofselecting the complement of an input if it is to be subtracted and ofselecting the proper value of the correction term. The input logicnetwork 124 is made up, as shown in FIGURE 16 of a plurality of andgates 164, 166, 168, 170, 172, 174, 176,178 and 180.

The terms (o and (01 are introduced to the and gate 164, the terms (67,,and (a are introduced to the and gate 166, the terms (6 and (11 areintroduced to the and gate 168, and the terms (6y) and (0: areintroduced to the and gate 170. The scanning term V is introduced to theand" gate 172, and the term Ra is introduced to that and gate. Thescanning term V is introduced to the and gate 174, and the term IE; isalso introduced to that and gate.

18' As described above, the correction term may be represented as:

( 2)n( z)nl 3)n( y)nl As described above, this correction term may be F)(:l:1)(i )(:l:1)

When the correction term (64) indicates that a +1 correction is to bemade, the term (C) from the logic of FIGURE 17 becomes true to enablethe and gate 176. This and gate causes a multi-digit binary signal froma suitable source representing (+1) to be passed to the preliminarysummer 150 of FIGURE 15.

In like manner, when the correction term (64) indicates that a -1correction is to be made, the term (C) from the logic of FIGURE 18becomes true to enable the and gate 178. The and gate then passes amultidigit binary signal corresponding to -1 from an appropriate sourceto the preliminary summer 150 in FIGURE 15. Likewise, then thecorrection term 64 indicates that a O correction is to be made, the term(0) from the logic of FIGURE 19 is true to enable the and gate 180. Thislatter and gate then passes a multi-digit binary signal firom anappropriate source and representing 0 to the preliminary summer 150.

The (C) selection logic of FIGURE 17 looks at all the combinations ofthe correction term (64) which indicate that a +1 correction should beintroduced into the Rea remainder register of FIGURE 14. If (1111 and (5are similar, and if (Aa and (8y) are dissimilar, a +1 correction isrequired. The logic expression for this is The terms T and (Ebareintroduced to the and gate 186; the terms (Aoc and (6 are introduced tothe and gate 188; the terms 3T and (a,,),, are introduced to the and.gate 192; and the terms (Aa and (5;) are introduced to the and gate 194.

In like manner, the (C) selection logic look at all the combinations ofthe correction formula which indicate that a 1 correction should beintroduced into the Rea remainder register 120 of FIGURE 14. If (41 and(8 are dissimilar, and if (11 and (6 are similar, then a 1 correction isrequired. The logical expression for this is The term (C) may bederived. by the logic illustrated in FIGURE 18. The illustrated logicalsystem includes an and gate 200 having a pair of or gates 202 and 204connected thereto. The and gate 200 is connected to the output terminal201 at which the term (C) is formed. A pair of and gates 206 and 208 isconnected to the or gate 202, and a pair of and gates 210 and 212 isconnected to the or gate 204.

The terms A 04 and (6,),, are introduced to the an gate 206; and theterms (Auc and (5;) i are introduced to the and gate 208. The terms(A0L3) and (5 :5 are introduced to the and gate 210, and the 19 terms(Aa and (6 are introduced to the and gate 212.

The (C) selection logic of FIGURE 19 looks at all the combinations ofthe correction formula 64 which indicate that the correction should. beintroduced into the R061 register 120 of FIGURE 14. The term (0) may bederived from the logic system illustrated in FIGURE 19 and whichincludes an or gate 220 connected to the output terminal 221 at whichthe term (C) is formed.

A pair of and gates 222 and 224 is connected to the or gate 220. A pairof or gates 226 and 228 is connected to the and gate 222, and a pair ofor gates 230 and 232 is connected to the and gate 224. A pair of and.gates 234 and 236 is connected to the or gate 228, and a pair of andgates 238 and 240 is connected to the or gate 228. A pair of and gates242 and 244 is connected to the or gate 230, and a pair of and gates 246and 248 is connected to the or gate 232.

The terms (Aoc and are introduced to the and gate 234, and the terms (T0 and are introduced to the and gate 236. The terms (Aot and (6 areintroduced to the and gate 238, and the terms (EL, and 6;), areintroduced to the and gate 240. The terms (Au;),, and (5) are introducedto the and gate 242, and. the terms (EL, and (6 are introduced to theand gate 244. The terms (Au and (6 are introduced to the and gate 246,and

the term-s AT and (6 are introduced to the and gate 248.

The logic illustrated in FIGURE 19 may be represented by the followinglogic equation:

The critical condition scanning logic 128 is shown in greater detail inFIGURE 20. As noted above, the input logic of RZFIGURE l6 performs thefunction of selecting the complement R of the output R from theremainder register 120 when the term V is true, and of selecting theoutput R directly if the term V is true.

The selection signal V from the critical condition scanning logic 128 isnormally high to permit the output R from the remainder register 120 inFIGURE 14 normally to circulate through the and gate 172 (FIGURE 16) ofthe input logic network 124 as an input to the fourinputadder-subtractor 122.

When the selection signal I7 from the critical condition scanning logic128 is high, it denotes that the scan in the m module has indicated theoccurrence of a critical condition (1.000 or 0.111 in the R remainderregister 120 of FIGURE 14 requiring that the number in the remainderregister 120 of FIGURE 14 be comple- Inented when it next enters theadder-subtractor 122. Should the corresponding check module alsoindicate a condition of criticality, the term C: is true, and the term Vbecomes true so that the overflow pulse (A01 from the remainder register12!) is complemented by the logic network 130 of FIGURE 14.

As will be explained in more detail in conjunction with FIGURE 23, thecorresponding check module compares the sum a +ot +ot with unity todetermine whether the sum is greater or less than 1. By simpletrigonometry, the sum should always be equal to 1 unless an error hasoccurred as mentioned above. Should a critical condition occur in eitheror both the m or 0: modules at the same time as a critical conditionoccurs in the 0: module of FIGURE 14, the term-s (m and (11 of FIGURE 16would be inaccurate. When such a condition occurs, the resulting sum a+a +0t in the corresponding check module isgreater. than 1, and thiscauses the term G; of

FIGURE 20 to become true. When that occurs, and a condition ofcriticality exists in the R remainder register of FIGURE 14, the term Ibecomes true so that the logic of FIGURE 14 can complement the resultingincrement (Ana so that it is effectively subtracted from, instead ofbeing added to, the content of the addend register 134 so that any errorin the 0: module due to the inaccuracies in the terms 1x or 0: iscorrected.

The criticality of the new remainder R in the remainder register 120 isdetermined by the critical condition scanning logic 128 during thegeneration of that remainder and prior to output to the addend register134, as described above; while the criticality of the new incrementpassing through the logic network 130 is established by thecorresponding check module at the time of output generation, so thatcompensation may be made to the addend register.

When the term V is true to indicate the condition of criticality in themodule a this term is used, as mentioned, to enable the and gate 174(FIGURE 16) in the input logic 124 so that bits of the word in theremainder register may be complemented as they are read out of theremainder register 120 for use during the following cycle.

The critical condition scanning logic 128 of FIGURE 20 includes a pairof and gates 250 and 252, and it includes a pair of flip-flops S1 andS2. The flip-flop S1 introduces its output term S1 to the and gate 250,and introduces its output term S 1 to the and gate 252. Likewise, theflip-flop S2 introduces its output term to the and gate 250 and 252. Theterm (C) from the logic circuitry of FIGURE 17 is introduced to the andgate 250. The term (C) from the logic circuitry of FIG- URE 18 isintroduced to the and gate 252.

An and gate 254 is coupled to the true input terminal of the fiip-fiopS1, and an and gate 256 is coupled to the false input terminal of thatflip-flop. The output terms A and A; from the adder 122 are introducedre spectively to the and gate 254 and 256. A bit timing pulse P is alsointroduced to these and gates so that the and gates are enabled only atthe first bit time of each compute cycle.

An or gate 258 is coupled to the true input terminal of the flip-flopS2, and a pair of and gates 260 and 262 is coupled to the or gate 258.The output term S1 from the flip-flop S1 is introduced to the and gate260, and the output term A from the adder 122 is also introduced to thatand gate. The term SI from the flip-flop S1 is introduced to the andgate 262, and the term A is also introduced to that and gate.

The and gates 250 and 252 are coupled to an or gate 264 which, in turn,is connected to the false input terminal of a flip-flop V included inthe scanning logic 128. A bit timing pulse P21 sets the flip-flop S2false at the end of each compute cycle, and the bit timing pulse P setsthe flip-flop V true at the beginning of the compute cycle.

The flip-flop V supplies the terms V and V to the input logic network124 of FIGURE 14. The term V is also introduced to an and gate 266, andthe term 6; from the corresponding check module is also introduced tothe and gate 266. The and gate 266 applies the term 7 to the logicnetwork 130 of FIGURE 14.

The bit timing pulse P in the logic associated with the S1 flip-floppermits this flip-flop to read only the least significant bit coming outof the adder 122. Subsequent outputs of the adder are compared to thestate of the flipfiop S1, by the input logic to the flip-flop S2. If theflipflop S2 is set high at the end of the compute cycle, it indicatesthat no critical condition exists. The bit timing pulse P21 resets theflip-flop S2 false prior to the next compute cycle.

Therefore, when the term is true at P20 bit time, it indicates that acritical condition occurs in the R re-

6. A SYSTEM FOR CONVERTING THE COORDINATES OF A VELOCITY VECTORREFERENCED TO A FIRST SET OF AXES IN A FIRST THREEDIMENSIONAL COORDINATESYSTEM TO CORRESPONDING COORDINATES REFERENCED TO A SECOND SET OF AXESIN A SECOND THREE-DIMENSIONAL COORDINATE SYSTEM, SAID CONVERTING SYSTEMINCLUDING: FIRST DIGITAL SENSOR MEANS FOR SENSING LINEAR CHANGES OF THECOORDINATES OF SAID VELOCITY VECTOR WITH RESPECT TO THE FIRST COORDINATESYSTEM AND FOR PRODUCING DIGITAL SIGNALS REPRESENTATIVE OF SUCH CHANGES;SECOND DIGITAL SENSOR MEANS FOR SENSING ANGULAR CHANGES BETWEEN THE AXESOF THE FIRST COORDINATE SYSTEM AND CORRESPONDING ONES OF THE AXES OF THESECOND COORDINATE SYSTEM AND FOR PRODUCING DITITAL SIGNALSREPRESENTATIVE THEREOF; FIRST MULTI-DIGIT BINARY INCREMENTAL COMPUTERMEANS COUPLED TO SAID SECOND SENSOR MEANS AND RESPONSIVE TO THE DIGITALSIGNALS THEREFROM FOR PRODUCING FIRST SIGNALS REPRESENTATIVE OFINCREMENTAL CHANGES IN THE COSINES OF THE ANGULAR DISPLACEMENTS OF THEAXES OF THE FIRST COORDINATE SYSTEM WITH RESPECT TO EACH OF THE AXES OFTHE SECOND COORDINATE SYSTEM, AND FOR PRODUCING SECOND SIGNALS FORCOMPENSATING ERRONEOUS GROWTHS IN SAID FIRST SIGNALS; SAID FIRSTINCREMENTAL COMPUTER MEANS INCLUDING A PLURALITY OF SECTIONS, EACHINCLUDING A REMAINDER REGISTER FOR ACCUMULATING THE LEAST SIGNIFICANTDIGITS OF A CORRESPONDING ONE OF SAID FIRST SIGNALS, AN ADDEND REGISTERFOR ACCUMULATING THE MOST SIGNIFICANT DIGITS OF THE CORRESPONDING ONE OFSAID FIRST SIGNALS, A CIRCULATING SYSTEM FOR SAID REMAINDER REGISTERINCLUDING MEANS FOR INTRODUCING OVERFLOW SIGNAL FROM SAID REMAINDERREGISTER TO SAID ADDEND REGISTER, SAID CIRCULATING SYSTEM FURTHERINCLUDING AN ADD-SUBTRACT NETWORK AND AN INPUT LOGIC NETWORK COUPLEDTHERETO, AND MEANS FOR INTRODUCING A CORRECTION SIGNAL DERIVED FROM ACORRESPONDING ONE OF SAID SECOND SIGNALS INTO SAID INPUT LOGIC NETWORKTO CORRECT A TENDENCY FOR THE SIGNALS ACCUMULATED IN SAID REMAINDERREGISTER TO GROW ERRONEOUSLY FOR SUCCESSIVE COMPUTE CYCLES OF SAID FIRSTINCREMENTAL COMPUTER MEANS, AND SECOND INCREMENTAL COMPUTER MEANSCOUPLED TO SAID FIRST DIGITAL SENSOR MEANS AND TO SAID FIRST INCREMENTALCOMPUTER MEANS AND RESPONSIVE TO SIGNALS THEREFROM PRODUCING OUTPUTSIGNALS REPRESENTATIVE OF CHANGES IN THE COORDINATES OF THE VELOCITYVECTOR WITH RESPECT TO THE AXES OF SAID SECOND COORDINATE SYSTEM.